In semiconductor storage devices such as a NAND flash EEPROM (Electrically Erasable Programmable Read-Only Memory), regions between adjacent memory cell arrays are conventionally used as bit-line contact regions. In each of the bit-line contact regions, a bit line in an upper layer is electrically connected to an active area via a contact plug. In these bit-line contact regions, a diffusion layer is formed for the contact plug to connect to the corresponding active area. The diffusion layer is formed in a high concentration similarly to a diffusion layer used for memory cells or transistors of peripheral circuits. Therefore, to form the diffusion layer, a high dose amount of impurities is ion-implanted into the active areas at a high acceleration energy.
However, when the distance (the bit-line contact region) between two select gate transistors adjacent to each other between the memory cell arrays is narrowed or when the distance between active areas is reduced, crystal defects in the active areas or deformations thereof due to impurity ion implantation become non-negligible. The crystal defect in the active area causes an increase in the contact resistance. Furthermore, the deformation of the active area causes a short circuit of the contact plug to an erroneous active area (another bit line).